to je tRAS.

viz https://www.gamersnexus.net/guides/3333-memory-timings-defined-cas-latency-trcd-trp-tras

Row Active Time (tRAS):

Wikipedia: “The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with tRCD. In SDRAM modules, it is simply tRCD + CL. Otherwise, approximately equal to tRCD + 2×CL.”

Also known as Activate to Precharge Delay or Minimum RAS Active Time.

edit: všimni si, že Aušus automaticky nasazuje nejagresivnější časování....